Simplify I2C Electrical Validation and Protocol Decode Using Software

Overview of I2C Bus:

In early 1980s Philips Semiconductor developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called Inter IC or I2C bus. All I2C Bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C -bus.

The I2C’s physical two-wire interface consists of a bi-directional serial clock (SCL) and data (SDA) lines. Each device that is connected to the bus is software-addressable by a unique address and simple master/slave relationship with the bus exists all the time. I2C is a serial, 8-bit oriented, bi-directional data transfers can be made at 100Kbits/s in the standard mode, up to 400Kbits/s in the Fast mode, up to 1Mbits/s in fast Mode plus, or up to 3.4Mbits/s in the high speed mode. On-chip filtering rejects spikes on the bus data line to preserve data integrity.

Phillips Semiconductor (now NXP Semiconductors) has published electrical specifications and protocol specification since 1982. The recent I2C- bus specification and user manual was published in year 2007. By following the electrical and protocol specification in the I2C document, semiconductor design and manufacturing companies can ensure interoperability of ICs using I2C Bus.

I2C protocol overview:

Typical data transfer between two ICs using the I2C interface is as shown:

All transactions start with START Condition and stop with STOP condition In I2C Bus. These two conditions are controlled by the master IC. The typical I2C frame format has the following contents: START, address, read/write, data followed by ACK/NACK, and STOP condition at end of the operation.

START: A condition where high to low transition of SDA line occurs when SCL is held high. The is initiated by the master IC.

Address: Master sends the slave the 7- bit or 10- bit address of the slave device

Read/write: The slave address is followed by this bit. A ZERO indicates a transmission (write), and a ‘ONE’ indicates a request for READ.

Acknowledge (ACK) and Not Acknowledge (NACK): This takes place after every byte. During this condition the transmitter releases the SDA line during the acknowledge clock pulse so that the receiver can pull the SDA line LOW, and the SDA line remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during this 9thclock pulse, this defined as the Not Acknowledgement signal. The master can then regenerate either a STOP condition to abort the transfer or a repeated START condition to start a new transfer.

Data is an integer number of bytes read or written into device.

STOP: A condition during SDA transitions from LOW to HIGH when SCL is held high indicating the end of transfer of data.

I2C Electrical Measurements:

For successful interoperation of IC using I2C bus, the electrical characteristics of physical layer signals of I2C SCL and SDA signals should be compatibility. The timing between the master and slave devices should be within electrical specifications defined in the I2C Specification by NXP Semiconductor.

Electrical Measurement Challenges:

During electrical validation of I2C bus, test engineers need to ensure the I2C bus should comply with electrical parameters of I2C Bus. The challenges faced while electrical validation of I2C bus as follows:

• Test/Design Engineer must know I2C Protocol behaviour at physical layer of I2C Bus

• Electrical parameter measurements must be carried out at different protocol state ( example; stop bit, ack bit and so forth)

• Reference level for each of the measurement changes based on the rising or falling edge of the I2C signal transition

• Reference level is either 30% or 70% as against normally used reference level of 10% to 90% or 20% to 80%

• Validation is time consuming

Overall, measuring I2C electrical measurements demands a very high level of expertise in I2C phy layer behaviour, protocol layer, signal acquisition in oscilloscope and I2C Electrical measurement procedures. Due to complexity in I2C Electrical measurements, the results can be prone to errors.

Simplifying I2C Electrical Measurements using PGY-I2C Electrical validation and Protocol Decode Software:

The PGY-I2C Electrical Validation and Protocol Decode Software offers electrical measurements and protocol decoding as specified in Rev 03, June 2007 I2C Bus specification. Now design and test engineers can automatically make accurate and reliable electrical measurements and decode protocols in PGY-I2C software using data acquired by Tektronix DPO5000, DPO7000, DPO/DSA/MSO70000 series oscilloscope to reduce the development and test cycle.

PGY-I2C Software runs inside Tektronix oscilloscopes. During the run operation of the application, PGY-I2C sends commands to acquire to SCL and SDA signals of I2C bus. For accurate measurements, the recommended oscilloscope setup is:

• Signal is at least 5 to 6 six main vertical divisions in the oscilloscope display with the appropriate volts per division

• Select the appropriate volts per division to display the signal with at least 5 or 6 main vertical divisions

• Select sample rate such that at least 8 to 10 samples present in the rising or falling edge of SCL and SDA signals

• Set record length such that at least two I2C frames are captured to make most of I2C signals.

The application makes each of the I2C electrical measurements in every possible I2C protocol state and displays the min, max and mean values. If mean value is within the limit specified, application shows ‘Pass’. But in case, if the mean value is pass but either the min or max values exceed the limits, applications shows ‘pass*’ with asterisk.

PGY-I2C makes all these measurements in an instant of time addressing all the challenges of I2C electrical measurements, giving accurate and reliable measurements.

The ‘Detail View’ in the Analyze pane offers protocol information and measurement for each I2C Packet. This would help in debugging I2C bus in a system. In a master-slave I2C bus, different ICs would communicate. There is possibility of interoperability issues between IC s using I2C Bus. This problem could be due following reasons.

• Problems due to signal integrity in PCB

• EMI/EMC issues

• Not strict compliance to electrical characteristics of I2C Standard specification

The ‘Detail view’ would help in isolating interoperability issues by providing physical layer waveform, electrical measurements for each I2C message/frame and protocol decode.

Detail view contains following information:

• Waveform plot of the acquired data

• Protocol Decode in I2C packet/frame or I2C message format

• Electrical measurements for each I2C message or I2C packet/frame

• Selected I2C message or packet/frame waveform plot with protocol decoded data overlapped on the waveform

• Utility features such as cursors, cursor time readout, zoom, undo, fit to screen and pan

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